View EL4584_1995742.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ? fn7174 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved. elantec is a registered trademark of elantec semiconductor, inc. all other trademarks mentioned are the property of their respective owners. EL4584 horizontal genlock, 4f sc the EL4584 is a pll (phase lock loop) sub system, designed for video applications but also suitable for general purpose use up to 36mhz. in a video application this device generates a ttl/cmos compatible pixel clock (clk out) which is a multiple of the tv horizontal scan rate, and phase locked to it. the reference signal is a horizontal sync signal, ttl/cmos format, which can be easily derived from an analog composite video signal with the el4583 sync separator. an input signal to ?coast? is provided for applications were periodic disturbances are present in the reference video timing such as vtr head switching. the lock detector output indicates correct lock. the divider ratio is four ratios for ntsc and four similar ratios for the pal video timing standards, by external selection of three control pins. these four ratios have been selected for common video applications including 4f sc , 3f sc , 13.5mhz (ccir 601 format) and square picture elements used in some workstation graphics. to generate 8f sc , 6f sc , 27mhz (ccir 601 format ) etc. use the el4585, which includes an additional divide by 2 stage. for applications where these fr equencies are inappropriate or for general purpose pll applications the internal divider can be bypassed and an external divider chain used. features 36mhz, general purpose pll 4f sc based timing (use the el4585 for 8f sc ) compatible w/el4583 sync separator vcxo, xtal, or lc tank oscillator < 2ns jitter (vcxo) user controlled pll capture and lock compatible with ntsc and pal tv formats 8 pre-programmed tv scan rate clock divisors selectable external divide for custom ratios single 5v, low current operation applications pixel clock regeneration video compression engine (mpeg) clock generator video capture or digitization pip (picture in picture) timing generator text or graphics overlay timing demo board a demo pcb is available for this product. request ?EL4584/5 demo board?. pinout frequencies and divisors function 3f sc (note 1) ccir 601 (note 2) square (note 3) 4f sc divisor 851 864 944 1135 pal fosc (mhz) 13.301 13.5 14.75 17.734 divisor 682 858 780 910 ntsc fosc (mhz) 10.738 13.5 12.273 14.318 notes: 1. 3f sc numbers do not yield integer divisors. 2. ccir 601 divisors yield 720 pixels in the portion of each line for ntsc and pal. 3. square pixels format gives 640 pixels for ntsc and 768 pixels for pal in the active portion. ordering information part number temp. range package pkg. no. EL4584cn -40c to +85c 16-pin dip mdp0031 EL4584cs -40c to +85c 16-pin so mdp0027 note: for 6f sc and 8f sc clock frequencies, see el4585 datasheet. EL4584 (16-pin so, pdip) top view data sheet february 1995, rev b
2 note: 1. all inputs to 0v, coast floating. note: 1. noisy video signal input to el4583, h-sync i nput to EL4584. test for positive signal lock. absolute maximum ratings (t a = 25c) v cc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v operating junction temp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400mw lead temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c oscillator frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36mhz pin voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v cc +0.5v operating ambient temperature range . . . . . . . . . .-40c to +85c caution: stresses above those listed in ?a bsolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a dc electrical specifications v dd = 5v, t a = 25c unless otherwise noted parameter conditions temp min typ max units i dd v dd = 5v (note 1) 25c 2 4 ma v il input low voltage 25c 1.5 v v ih input high voltage 25c 3.5 v i il input low current all inputs except coast, v in = 1.5v 25c -100 na i ih input high current all inputs except coast, v in = 3.5v 25c 100 na i il input low current coast pin, v in = 1.5v 25c -100 -60 a i ih input high current coast pin, v in = 3.5v 25c 60 100 a v ol output low voltage lock det, i ol = 1.6ma 25c 0.4 v v oh output high voltage lock det, i oh = -1.6ma 25c 2.4 v v ol output low voltage clk, i ol = 3.2ma 25c 0.4 v v oh output high voltage clk, i oh = -3.2ma 25c 2.4 v v ol output low voltage osc out, i ol = 200a 25c 0.4 v v oh output high voltage osc out, i oh = -200a 25c 2.4 v i ol output low current filter out, v out = 2.5v 25c 200 300 a i oh output high current filter out, v out = 2.5v 25c -300 -200 a i ol /i oh current ratio filter out, v out = 2.5v 25c 1.05 1.0 0.95 i leak filter out coast mode, v dd > v out > 0v 25c -100 1 100 na ac electrical specifications v dd = 5v, t a = 25c unless otherwise noted parameter conditions temp min typ max units vco gain @ 20mhz test circuit 1 25c 15.5 db h-sync s/n ratio v dd = 5v (note 1) 25c 35 db jitter vcxo oscillator 25c 1 ns jitter lc oscillator (typ) 25c 10 ns EL4584
3 pin descriptions pin no. pin name function 16,1,2 prog a,b,c digital inputs to select n value for internal counter. see table below for values. 3 osc/vco out output of internal inverter/oscillator. connect to external crystal or lc tank vco circuit. 4v dd (a) analog positive supply for oscillator, pll circuits. 5 osc/vco in input from external vco. 6v ss (a) analog ground for osci llator, pll circuits. 7 charge pump out connect to loop filter. if t he h-sync phase is l eading or h-sync frequenc y > clk n, current is pumped into th e filter capacitor to incr ease vco frequency. if h-sync phase is laggi ng or frequency < clk n, current is pumped out of the filter capacitor to decrease vco fr equency. during coast mode or when locked, charge pump goes to a high impedance state. 8 div select divide select input. when high, the internal di vider is enabled and ext div becom es a test pin, outputting clk n. when low, the internal divider is disabled and ext div is an input from an external n. 9 coast tri-state logic input. low(<1/3*v cc ) = normal mode, hi z (or 1/3 to 2/3*v cc ) = fast lock mode, high(>2/3*v cc ) = coast mode. 10 h-sync in horizontal sync pulse (cmos level) input. 11 v dd (d) positive supply for digital, i/o circuits. 12 lock det lock detect output. low level when pll is locked. pulses high when out of lock. 13 ext div external divide input w hen div sel is low, internal n output when div sel is high. 14 v ss (d) ground for digital, i/o circuits. 15 clk out buffered output of the vco. vco divisors table 1 prog a pin 16 prog b pin 1 prog c pin 2 div value n 000851 001864 010944 0 1 1 1135 100682 101858 110780 111910 EL4584
4 timing diagrams figure 1. pll locked condition (phase error = 0) falling edge of h- sync + 110ns locks to rising edge of ext div signal. figure 2. out of lock condition e = (t / t h ) 360 t h = h-sync period t = phase error period figure 3. test circuit 1 EL4584
5 typical performance curves block diagram idd vs fosc 4584 osc gain @ 20mhz vs temp typical varactor osc gain vs fosc charge pump duty cycle vs e EL4584
6 description of operation the horizontal sync signal (cmos level, falling leading edge) is input to h-sync input (pin 10). this signal is delayed about 110ns, the falling edge of which becomes the reference to which the clock output will be locked. (see timing diagrams.) the clock is generated by the signal on pin 5, osc in. there are 2 general types of vco that can be used with the EL4584, lc and crystal controlled. additionally, each type can be either built up using discrete components, including a varactor as the frequency controlling element, or complete, self contained modules can be purchased with everything inside a metal can. the modules are very forgiving of pcb layout, but cost more than discrete solutions. the vco or vcxo is used to generate the clock. an lc tank resonator has greater ?pull? than a crystal controlled circuit, but will also be more likely to drift over time, and thus will generate more jitter. the ?pullab ility? of the circuit refers to the ability to ?pull? the frequency of oscillation away from its center frequency by modulating the voltage on the control pin of a vco module or varactor, and is a function of the slope and range of the capacitance-voltage curve of the varactor or vco module used. the vco signal is sent to a divide by n counter, and to the clk out pin. the divisor n is determined by the state of pins 1,2, and 16 and is described in table 1 above. the divided signal is sent, along with the delayed hsync input, to the phase/frequency detector, which compares the two signals for phase and frequency differences. any phase difference is converted to a current at the charge pump output filter (pin 7). a vco with positive frequency deviation with control voltage must be used. varactors have negative capacitance slope with voltage, resulting in positive frequency de viation with control voltage for the oscillators in figures 10 and 11. vco the vco should be tuned so it s frequency of oscillation is very close to the required clock output frequency when the voltage on the varactor is 2.5 volts. vcxo and vco modules are already tuned to the desired frequency, so this step is not necessary if using one of these units. the range of the charge pump output (pin 7) is 0 to 5 volts and it can source or sink a maximum of about 300a, so all frequency control must be accomplished with variable capacitance from the varactor within this range. crys tal oscillators ar e more stable than lc oscillators, which translates into lower jitter, but lc oscillators can be pulled from their mid-point values further, resulting in a greater capture and locking range. if the incoming horizontal sync signal is known to be very stable, then a crystal oscillator circuit can be used. if the h-sync signal experiences frequency variations of greater than about 300ppm, an lc oscillat or should be considered, as crystal oscillators are very difficult to pull this far. when h- sync input frequency is greater than clk frequency n, charge pump output (pin 7) s ources current into the filter capacitor, increasing the voltage across the varactor, which lowers its capacitance, thus tending to increase vco frequency. conversely, filter output pulls current from the filter capacitor when h-sync frequency is less than clk n, forcing the vco frequency lower. loop filter the loop filter controls how fast the vco will respond to a change in filter output stimul us. its components should be chosen so that fast lock can be achieved, yet with a minimum of vco ?hunting?, preferably in one to two oscillations of charge pump output, assuming the vco frequency starts within capture range. if the filt er is under-damped, the vco will over and under-shoot the desired operating point many times before a stable lock takes place. it is possible to under- damp the filter so much that the loop itself oscillates, and vco lock is never achieved. if the filter is over-damped, the vco response time will be excessive and many cycles will be required for a lock condition. over-damping is also characterized by an easily unlocked system because the filter can?t respond fast enough to perturbations in vco frequency. a severely over damped system will seem to endlessly oscillate, like a very large mass at the end of a long pendulum. due to parasitic effects of pcb traces and component variables, it will take some trial and error experimentation to determine the best values to use for any given situation. use the com ponent tables as a starting point, but be aware that deviation from these values is not out of the ordinary. external divide div sel (pin 8) controls the use of the internal divider. when high, the internal divider is enabled and ext div (pin 13) outputs the clk out divided by n. this is the signal to which the horizontal sync input will lock. when divide select is low, the internal divider output is disabled, and external divide becomes an input from an external divider, so that a divisor other than one of the 8 pre-programmed internal divisors can be used. normal mode normal mode is enabled by pulling coast (pin 9) low (below 1/3*v cc ). if h-sync and clk n have any phase or frequency difference, an error signal is generated and sent to the charge pump. the charge pump will either force current into or out of the filt er capacitor in an attempt to modulate the vco frequency. modulation will continue until the phase and frequency of clk n exactly match the h- sync input. when the phase and frequency match (with some offset in phase that is a function of the vco characteristics), the error signal goes to zero, lock detect no longer pulses high, and the charge pump enters a high impedance state. the clock is now locked to the h-sync input. as long as phase and frequency differences remain small, the pll can adjust the vco to remain locked and lock detect remains low. EL4584
7 fast lock mode fast lock mode is enabled by either allowing coast to float, or pulling it to mid supply (between 1/3 and 2/3*v cc ). in this mode, lock is achieved much faster than in normal mode, but the clock divisor is modified on the fly to achieve this. if the phase detector detects an error of enough magnitude, the clock is either inhibited or reset to attempt a ?fast? lock of the signals. forcing the clock to be synchro nized to the h-sync input this way allows a lock in approximately 2 h-cycles, but the clock spacing will not be regular during this time. once the near lock condition is attained, charge pump output should be very close to its lock-on value and placing the device into normal mode should result in a normal lock very quickly. fast lock mode is intended to be used where h-sync becomes irregular, until a stable signal is again obtained. coast mode coast mode is enabled by pulling coast (pin 9) high (above 2/3*v cc ). in coast mode the internal phase detector is disabled and filter out remains in high impedance mode to keep filter out voltage and vco frequency as constant a possible. vco frequency will drift as charge leaks from the filter capacitor, and the volt age changes the vco operating point. coast mode is intended to be used when noise or signal degradation result in loss of horizontal sync for many cycles. the phase detector will not attempt to adjust to the resultant loss of signal so that when horizontal sync returns, sync lock can be re-established quickly. however, if much vco drift has occurred, it may take as long to re-lock as when restarting. lock detect lock detect (pin 12) will go low when lock is established. any dc current path from charge pump out will skew ext div relative to hsync in, tending to offset or add to the 110ns internal delay, depending on which way the extra current is flowing. this offset is called static phase error, and is always present in any pll system. if, wh en the part stabilizes in a locked mode, lock detect is not low, adding or subtracting from the loop filter series resistor r 2 will change this static phase error to allow ldet to go low while in lock. the goal is to put the rising edge of ext div in sync with the falling edge of h-sync + 110ns. (see timing diagrams.) increasing r 2 decreases phase error, while decreasing r 2 increases phase error. (phase error is positive when ext div lags hsync.) the resistance needed will depend on vco design or vcxo module selection. applications information choosing external components 1. to choose lc vco components, first pick the desired operating frequency. for our example we will use 14.31818mhz, with an h-sync frequency of 15.734khz. 2. choose a reasonable inductor value (10?20h works well). we choose 15h. 3. calculate c t needed to produce f osc . 4. from the varactor data sheet find c v @ 2.5v, the desired lock voltage. c v = 23pf for our smv1204-12, for example. 5. c 2 should be about 10c v , so we choose c 2 = 220pf for our example. 6. calculate c 1 . since then for our example, c 1 = 14pf. (a trim cap may be used for fine tuning.) examples for each frequency using the internal divider follow. typical application horizontal genlock provides clock for an analog to digital converter, digitizing analog video. f osc 1 2 lc t ---------------------- - = c t 1 4 2 f 2 l -------------------- - 1 4 2 14.318e6 () 2 15e 6 ? () --------------------------------------------------------------------- 8.2pf == = c t c 1 c 2 c v c 1 c 2 () c 1 c v () c 2 c v () ++ ---------------------------------------------------------------------------- = c 1 c 2 c t c v c 2 c v () c 2 c t () c t c v () ? ? ------------------------------------------------------------------------- - = figure 4. typical lc vco EL4584
8 the above oscillators are arranged as colpitts oscillators, and the structure is redrawn here to emphasize the split capacitance used in a colpitts oscillator. it should be noted that this oscillator configurat ion is just one of literally hundreds possible, and the c onfiguration shown here does not necessarily represent the best solution for all applications. crystal manufacturers are very informative sources on the design and use of oscillators in a wide variety of applications, and the reader is encouraged to become familiar with them. c 1 is to adjust the center frequency, c 2 dc isolates the control from the oscillator, and v1 is the primary control device. c 2 should be much larger than c v so that v 1 has maximum modulation capability. the frequency of oscillation is given by: choosing loop filter components the pll, vco, and loop filter can be described as: where: k d = phase detector gain in a/rad f(s) = loop filter impedance in v/a k vco = vco gain in rad/s/v n = internal or external divisor it can be shown that for the loop filter shown below: where ? n = loop filter bandwidth, and = loop filter damping factor. 1. k d = 300a/2 rad = 4.77e-5a/rad for the EL4584. 2. the loop bandwidth should be about h-sync frequency/20, and the damping ratio should be 1 for optimum performance. for our example, ? n = 15.734khz/20 = 787hz 5000rad/s. lc vco component values (approximate) (note) frequency (mhz) l1 (h) c1 (pf) c2 (pf) 13.301 15 18 220 13.5 15 17 220 14.75 12 18 220 17.734 12 10 220 10.738 22 20 220 12.273 18 17 220 14.318 15 14 220 note: use shielded inductors for optimum performance. xtal vco component values (approximate) frequency (mhz) r1 (k ? ) c1 (pf) c2 (f) 13.301 300 15 .001 13.5 300 15 .001 14.75 300 15 .001 17.734 300 15 .001 10.738 300 15 .001 12.273 300 15 .001 14.318 300 15 .001 figure 5. typical xtal vco figure 6. colpitts oscillator f 1 12 lc t -------------------------- = c t c 1 c 2 c v c 1 c 2 () c 1 c v () c 2 c v () ++ -------------------------------------------------------------------------- = c 3 k d k vco n 2 n ----------------------- - c 4 , c 3 10 ------ - r 3 , 2n n k d k vco ----------------------- - === EL4584
9 3. n = 910 from table 1. 4. k vco represents how much the vco frequency changes for each volt applied at the control pin. it is assumed (but probably isn?t) linear about the lock point (2.5v). its value depends on the vco configur ation and the varactor transfer function c v = f(v c ), where v c is the reverse bias control voltage, and c v is varactor capacitance. since f(v c ) is nonlinear, it is probably best to build the vco and measure k vco about 2.5v. the results of one such measurement are shown below. the slope of the curve is determined by linear regression techniques and equals k vco . for our example, k vco = 6.05 mrad/s/v. 5. now we can solve for c 3 , c 4 , and r 3 . we choose r 3 = 30k ? for convenience. 6. notice r 2 has little effect on the loop filter design. r 2 should be large, around 100k, and can be adjusted to compensate for any static phase error t at lock, but if made too large, will slow loop response. if r 2 is made smaller, t (see timing diagrams) increases, and if r 2 increases, t decreases. for ldet to be low at lock, |t |<50ns. c 4 is used mainly to attenuate high frequency noise from the charge pump. lock time let = r 3 c 3 . as t increases, damping increases, but so does lock time. decreasing t decreases damping and speeds up loop response, but increases overshoot and thus increases the number of hunting oscillations before lock. critical damping ( = 1) occurs at minimum lock time. because decreased damping also decreases loop stability, it is sometimes desirable to design slightly overdamped ( > 1), trading lock time for increased stability. pcb layout considerations it is highly recommended that power and ground planes be used in layout. the oscillator a nd filter sections constitute a feedback loop and thus care must be taken to avoid any feedback signal influencing the oscillator except at the control input. the entire oscillator/filter section should be surrounded by copper ground to prevent unwanted influences from nearby signals. use separate paths for analog and digital supplies, keeping the analog (oscillator section) as short and free from spurious signals as possible. careful attention must be paid to correct bypassing. keep lead lengths short and place bypass caps as close to the supply pins as possible. if laying out a pcb to use discrete components for the vco section, care must be taken to n vcofrequency h syncfrequency ? ---------------------------------------------------------- 14.31818m 15.73426k ----------------------------- - 910 === f osc vs v c , lc vco c 3 k d k vco n 2 n ----------------------- - 4.77e 5 ? () 6.05e6 () 910 () 5000 () 2 ----------------------------------------------------- - 0.01f == = c 4 c 3 10 ------ - 0.0001f == r 3 2n ? n k d k vco ----------------------- - 2 () 910 () 1 () 5000 () 4.77e 5 ? () 6.05e6 () ----------------------------------------------------- - 31.5k ? == = lc loop filter comp onents (approximate) frequency (mhz) r2 (k ? ) r3 (k ? ) c3 (f) c4 (f) 13.301 100 30 0.01 0.001 13.5 100 30 0.01 0.001 14.75 100 33 0.01 0.001 17.734 100 39 0.01 0.001 10.738 100 22 0.01 0.001 12.273 100 27 0.01 0.001 14.318 100 30 0.01 0.001 xtal loop filter components (approximate) frequency (mhz) r2 (k ? ) r3 (m ? ) c3 (pf) c4 (pf) 13.301 100 4.3 68 6.8 13.5 100 4.3 68 6.8 14.75 100 4.3 68 6.8 17.734 100 4.3 68 6.8 10.738 100 4.3 68 6.8 12.273 100 4.3 68 6.8 14.318 100 4.3 68 6.8 figure 7. typical loop filter EL4584
10 avoid parasitic capacitance at the osc pins 3 and 5, and filter out (pin 7). remove ground and power plane copper above and below these traces to avoid making a capacitive connection to them. it is also recommended to enclose the oscillator section within a shielded cage to reduce external influences on the vco, as they tend to be very sensitive to ?handwaving? influences, the lc variety being more sensitive than crystal controlled oscillators. in general, the higher the operating frequency, the more important these considerations are. self contained vcxo or vco modules are already mounted in a shielding cage and therefore do not require as much consideration in layout. many crystal manufacturers publish inform ative literature regarding use and layout of oscillators which should be helpful. demo board EL4584
11 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com the vco and loop filter section of the el4583/4/5 demo board can be implemented in the following configurations: component sources inductors dale electronics e. highway 50 po box 180 yankton, sd 57078-0180 (605) 665-9301 crystals, vcxo, vco modules connor-winfield 2111 comprehensive drive aurora, il 60606 (708) 851-4722 piezo systems 100 k street po box 619 carlisle, pa 17013 (717) 249-2151 reeves-hoffman 400 west north street carlisle, pa 17013 (717) 243-5929 saronix 151 laura lane palo alto, ca 94043 (415) 856-6900 standard crystal 9940 baldwin place el monte, ca 91731 (818) 443-2121 varactors alpha industries 20 sylvan road woburn, ma 01801 (617) 935-5150 motorola semiconductor products 2100 e. elliot tempe, az 85284 (602) 244-6900 note: these sources are provided for information purposes only. no endorsement of these companies is implied by this listing. (1) vcxo (2) xtal (3) lc tank EL4584

▲Up To Search▲

Price & Availability of EL4584

	To Download EL4584 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .